Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In bootstrap_build master-arm-bootstrap_debug, after:
  | 11 commits in gcc
  | 6abaf53d84db LoongArch: fix par_const_vector_shf_set_operand for vshuf4i [PR 126200]
  | 15fd8d8b5b5b RISC-V: Split the pr112431-13 test in to 2 file
  | c33b7b995f9c RISC-V: Add test cases for vfwcvtu.xu.f.v reg overlap
  | fc3efdeb72ac RISC-V: Add test cases for vfcvt.x.f.v reg overlap
  | 13fa720ce146 RISC-V: Allow RVV register overlap for vfwcvt.x[u].f.v
  | ... and 6 more commits in gcc

Produces Success:
  | Results changed to
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_debug:
  | 1
  | 
  | From
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_debug:
  | 1

Used configuration :
 *CI config* tcwg_bootstrap_build master-arm-bootstrap_debug
 *configure and test flags:* none, autodetected on armv8l-unknown-linux-gnueabihf

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:

You can find the failure logs in
 * http://54.172.246.49:9090/jobs/tcwg_bootstrap_build--master-arm-bootstrap_debug-build/builds/10106/archive/artifacts/
The full lists of regressions and improvements as well as configure and make commands are in
 * http://54.172.246.49:9090/jobs/tcwg_bootstrap_build--master-arm-bootstrap_debug-build/builds/10106/archive/artifacts/notify/

Current build   : http://54.172.246.49:9090/jobs/tcwg_bootstrap_build--master-arm-bootstrap_debug-build/builds/10106/archive/artifacts/
Reference build : http://54.172.246.49:9090/jobs/tcwg_bootstrap_build--master-arm-bootstrap_debug-build/builds/10105/archive/artifacts/