Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In  arm-linux-gnueabihf cross, after:
  | 15 commits in gcc
  | fd7c5910162a aarch64: Treat all SVE as basic NEON instructions in DFA
  | dfba6b52f5cd i386: Enable extendvNhfvNsf2 and truncvNsfvNhf2 for N 4, 8, 16 even for F16C or AVX512VL [PR121688]
  | cebcce44cccc [RISC-V][PR 127813] Add more czero patterns/splitters for RISC-V
  | 17f674dbbced config: sync with binutils-gdb
  | 93bcb5098e39 modula-2, make: Do not declare m2.pod .INTERMEDIATE
  | ... and 10 more commits in gcc


Used configuration :
 *CI config* tcwg_gnu_cross_check_gcc arm-linux-gnueabihf cross
 *configure and test flags:* --target arm-linux-gnueabihf --disable-multilib --with-float=hard --with-fpu=vfpv3-d16 --with-mode=thumb --with-tune=cortex-a9 --with-arch=armv7-a

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:

You can find the failure logs in *.log.1.xz files in
 * http://54.172.246.49:9090/jobs/tcwg_gnu_cross_check_gcc--master-arm-build/builds/10517/archive/artifacts/00-sumfiles/
The full lists of regressions and improvements as well as configure and make commands are in
 * http://54.172.246.49:9090/jobs/tcwg_gnu_cross_check_gcc--master-arm-build/builds/10517/archive/artifacts/notify/
The list of [ignored] baseline and flaky failures are in
 * http://54.172.246.49:9090/jobs/tcwg_gnu_cross_check_gcc--master-arm-build/builds/10517/archive/artifacts/sumfiles/xfails.xfail

Current build   : http://54.172.246.49:9090/jobs/tcwg_gnu_cross_check_gcc--master-arm-build/builds/10517/archive/artifacts/
Reference build : http://54.172.246.49:9090/jobs/tcwg_gnu_cross_check_gcc--master-arm-build/builds/10514/archive/artifacts/