Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In simplebootstrap_build master-arm-bootstrap, after:
  | 12 commits in gcc
  | 599ee740f99f RISC-V: Add test cases for vzext.vf2 reg overlap
  | 92d99e6484ae RISC-V: Add test cases for vsext.vf2 reg overlap
  | 98fa7681e728 RISC-V: Allow RVV register overlap for v[sz]ext.vf2
  | 9e79c831aec0 Daily bump.
  | cc2a9b13bbf9 c++: handle nullptr_t in can_convert_eh
  | ... and 7 more commits in gcc

Produces Success:
  | Results changed to
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap:
  | 1
  | 
  | From
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap:
  | 1

Used configuration :
 *CI config* tcwg_simplebootstrap_build master-arm-bootstrap
 *configure and test flags:* none, autodetected on armv8l-unknown-linux-gnueabihf

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:

You can find the failure logs in
 * http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10187/archive/artifacts/
The full lists of regressions and improvements as well as configure and make commands are in
 * http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10187/archive/artifacts/notify/

Current build   : http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10187/archive/artifacts/
Reference build : http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10186/archive/artifacts/