Dear contributor,

Our automatic CI successfully passed with your patch(es). Please find some details below.

In simplebootstrap_build master-arm-bootstrap, after:
  | 26 commits in gcc
  | be751fc9fb5 RISC-V: Adjust test case due to allow vwcvt[u].x.x.v overlap
  | df635aadf0f RISC-V: Add test cases for vwcvtu.x.x.v reg overlap
  | df28d04aa00 RISC-V: Add test cases for vwcvt.x.x.v reg overlap
  | 5d98400b5a7 RISC-V: Allow RVV register overlap for vwcvt[u].x.x.v
  | f81f033bdfd contrib: Fix exit status of relpath.sh for invalid args [PR125956]
  | ... and 21 more commits in gcc

Produces Success:
  | Results changed to
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap:
  | 1
  | 
  | From
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap:
  | 1

Used configuration :
 *CI config* tcwg_simplebootstrap_build master-arm-bootstrap
 *configure and test flags:* none, autodetected on armv8l-unknown-linux-gnueabihf

If you have any questions regarding this report, please ask on linaro-toolchain@lists.linaro.org mailing list.

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The information below contains the details of the failures, and the ways to reproduce a debug environment:

You can find the failure logs in
 * http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10209/archive/artifacts/
The full lists of regressions and improvements as well as configure and make commands are in
 * http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10209/archive/artifacts/notify/

Current build   : http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10209/archive/artifacts/
Reference build : http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-build/builds/10208/archive/artifacts/