Commit: See in git+ssh://linaroci@gcc.gnu.org/git/gcc.git
gcc patch https://patchwork.sourceware.org/patch/138545
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Mon Jul 6 18:03:26 2026 +0800

    [PATCH] middle-end: keep _BitInt padding bits extended across atomic RMW [PR124948]
    
    Some targets (riscv, arm) specify in their psABI that the padding bits of
    a _BitInt(N) value (the bits above N up to the container width) are sign or
    zero extended, and advertise this via bitint_info::extended == bitint_ext_full
... 55 lines of the commit log omitted.
... applied on top of baseline commit:
30fa32b2bff [PATCH] RISC-V: Fix ext-dce-4.c test_half_sign_needed shift amount

* tcwg_simplebootstrap_build
** master-arm-bootstrap
*** Success
*** https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/67203646b585be3b598a60677f8513b32f97108d/tcwg_simplebootstrap_build/master-arm-bootstrap/details.txt
*** http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-precommit/builds/10961/archive/artifacts/

Latest data: https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/67203646b585be3b598a60677f8513b32f97108d/jira/yaml