Commit: See in git+ssh://linaroci@gcc.gnu.org/git/gcc.git gcc patch https://patchwork.sourceware.org/patch/141821 Author: Kito Cheng Date: Thu Aug 20 18:30:28 2026 +0800 [to-be-committed] RISC-V: Fix ICE passing an empty aggregate under the VLS calling convention riscv_flatten_aggregate_argument returns 0 for an aggregate with no field, but riscv_pass_aggregate_in_vr only rejected -1 and then read fields[0], which was never written: ... 20 lines of the commit log omitted. ... applied on top of baseline commit: 48425ec4ef2 aarch64: implement ctz2 for the Advanced SIMD byte and halfword modes * tcwg_simplebootstrap_build ** master-arm-bootstrap *** Success *** https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/6e6b1b8296e04852d44084570d10de3cced8bc2d/tcwg_simplebootstrap_build/master-arm-bootstrap/details.txt *** http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-precommit/builds/12376/archive/artifacts/ Latest data: https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/6e6b1b8296e04852d44084570d10de3cced8bc2d/jira/yaml