Commit: See in git+ssh://linaroci@gcc.gnu.org/git/gcc.git
gcc patch https://patchwork.sourceware.org/patch/142620
Author: Orgad Shaneh <orgads@gmail.com>
Date:   Tue Sep 1 10:54:49 2026 +0000

    [PATCH] mips: Disallow eliminable registers in the indexed-load patterns [PR127161]
    
    combine can form the L{B,H,W,D}{,U}X and LWXS patterns with the soft
    frame pointer as the address base (an indexed load from a stack
    object).  The reg+reg address embedded in those patterns is not
... 31 lines of the commit log omitted.
... applied on top of baseline commit:
c500635955c AVR: Skip gcc.dg/pr28796-2.c

* tcwg_simplebootstrap_build
** master-arm-bootstrap
*** Success
*** https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/301d0c3b3d2dbf5dec7ec07736de35062d8d2d2c/tcwg_simplebootstrap_build/master-arm-bootstrap/details.txt
*** http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-precommit/builds/12797/archive/artifacts/

Latest data: https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/301d0c3b3d2dbf5dec7ec07736de35062d8d2d2c/jira/yaml