Commit: See in git+ssh://linaroci@gcc.gnu.org/git/gcc.git
gcc patch https://patchwork.sourceware.org/patch/146260
Author: Alexey Lapshin <alexey.lapshin@espressif.com>
Date:   Mon Oct 19 13:15:23 2026 +0700

    [PATCH] xtensa: Model SAR as a hard register
    
    Previously, omitting a redundant SAR setup was only done for consecutive
    bswapsi2_internal insns (SSAI 8) in the same basic block.  Every other
    shift, funnel-shift, and rotate emitted SSL, SSR, SSAI, SSA8B, or SSA8L
... 111 lines of the commit log omitted.
... applied on top of baseline commit:
a358686eca1 i386: Do not clobber DRAP register during stack probing

* tcwg_simplebootstrap_build
** master-arm-bootstrap
*** Success
*** https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/6aa04e6b283ed0de9bc635b5b3034e7884dd32cd/tcwg_simplebootstrap_build/master-arm-bootstrap/details.txt
*** http://54.172.246.49:9090/jobs/tcwg_simplebootstrap_build--master-arm-bootstrap-precommit/builds/14070/archive/artifacts/

Latest data: https://gitlab.com/LinaroLtd/tcwg/ci/interesting-commits/-/raw/master/gcc/sha1/6aa04e6b283ed0de9bc635b5b3034e7884dd32cd/jira/yaml